Conventionally, a plasma processing apparatus such as an etching processing apparatus has been widely used in, e.g., a manufacturing process of, e.g., a fine electric circuit of a semiconductor device.
In such a plasma processing apparatus, a substrate to be processed, e.g., a semiconductor wafer, is disposed in a processing chamber whose inner space is configured to be capable of being airtightly sealed, and a plasma is generated in the processing chamber to be applied to the substrate to be processed to be used in performing a plasma process such as an etching.
Further, the plasma processing apparatus may include an annular member called a focus ring disposed to surround a semiconductor wafer serving as a substrate to be processed. The focus ring is installed, for example, for the purpose of confining a plasma, ameliorating discontinuity in a bias potential in a surface of the semiconductor wafer due to a fringing effect and performing a uniform and satisfactory process at a peripheral portion of the semiconductor wafer as well as at a central portion thereof.
There is known a plasma processing apparatus configured to prevent reactant species in a plasma from being concentrated around a lower electrode and reduce a processing speed at the peripheral portion of the semiconductor wafer, wherein the focus ring is disposed to surround the semiconductor wafer as described above, and a dielectric is disposed to be in contact with the plasma to thereby displace the plasma upward in an axial direction to be kept away from the lower electrode (see, for example, Reference Patent 1).
Further, as mentioned above, one of the purposes of the focus ring is to reduce the discontinuity in the bias potential. Thus, conventionally, a surface (top surface) of the focus ring and a surface of a semiconductor wafer to be processed are set to be on a substantially same plane, that is, at an approximately same height; the surface (top surface) of the focus ring is set to be higher than the surface to be processed of the semiconductor wafer; or a material of the focus ring is selectively chosen to help reducing the discontinuity in the bias potential (see, for example, Reference Patent 2).
[Reference Patent 1]
Japanese Patent Laid-open Application No. 2001-516948 (pages 13 to 41, FIGS. 1 to 7)
[Reference Patent 2]
Japanese Patent Laid-open Application No. 2003-503841 (pages 12 to 22, FIGS. 2 to 6)
As described above, a focus ring is conventionally used in a plasma processing apparatus to improve uniformity of a process.
FIG. 15 illustrates an example of a conventional focus ring, wherein an annular focus ring 101 made of a conductive material such as silicon is disposed on a susceptor 100 also serving as a low electrode to surround a semiconductor wafer W, i.e., a substrate to be processed.
Moreover, in the example illustrated in FIG. 15, a top surface of the focus ring 101 is of a height approximately identical to that of a surface to be processed (surface) of the semiconductor wafer W. As a result, an electric field above the focus ring 101 becomes approximately identical to that above the surface of the semiconductor wafer W, whereby reducing discontinuity in a bias potential due to a fringing effect. Thus, as shown by a dotted line in the drawing, a plasma sheath over the surface of the semiconductor wafer W and that over the focus ring 101 become of an approximately same height. By such a plasma sheath, as indicated by arrows in the drawing, incident ions fall vertically on the surface of the semiconductor wafer W even in a peripheral portion of the semiconductor wafer W.
However, using the focus ring 101 may result in a so-called deposition, in which undesirable deposits made of CF-based polymer and the like are adhered to a backside surface of the peripheral portion (edge portion) of the semiconductor wafer W.
A careful research on a cause of the deposition has resulted in a following conjecture. When using the above focus ring 101, the semiconductor wafer W and the focus ring 101 are approximately of a same potential and, thus, an electric field whose electric lines of force are indicated by dotted lines in an enlarged view of FIG. 16 is formed between the peripheral portion (edge portion) of the semiconductor wafer W and an inner peripheral portion of the focus ring 101. Accordingly, as indicated by solid arrows in the drawing, the plasma can easily reach the backside surface of the semiconductor wafer W through a portion between the peripheral portion (edge portion) of the semiconductor wafer W and the inner peripheral portion of the focus ring 101. Therefore, it seems that the deposition occurs on the backside surface of the peripheral portion (edge portion) of the semiconductor wafer W by the plasma that reaches the backside surface of the semiconductor wafer W.